1. Field of the Invention
The present invention relates to a flip-flop arrangement and, more particularly, to a delay type flip-flop (D-F.F.) arrangement using a transistor transistor logic (TTL). The D-F.F. arrangement according to the present invention can be utilized, for example, as an output flip-flop in a programmable read only memory additionally having a function of an output register.
2. Description of the Related Art
A known typical D-F.F. arrangement includes an input buffer, a master F.F. responding to a clock signal fed via the input buffer and an input data, a slave F.F. responding to an output of the master F.F., and an output buffer responding to an output of the slave F.F. According to the arrangement, the master F.F. carries out its flip-flop operation when the clock signal is at a predetermined logical level and transmits a change in the input data to the slave F.F., where the data is latched. The output buffer effects a buffering of the data latched in the slave F.F. and outputs the buffered data as a logical output of the arrangement.
That is to say, each of three gates from the master F.F. through the output buffer is activated by the output of the preceding gate. Therefore, the total propagation delay time required from when the clock signal is changed in logical level until when the logical output is settled in logical level is indicated by the sum of propagation delay time in each of four gates. In this case, it would be preferable to improve a circuit constitution and to reduce the total propagation delay time as short as possible.
On the other hand, in order to increase the operation speed in the D-F.F. arrangement, it is considered to decrease a resistance in each gate and, accordingly, to increase the amount of currents flowing therein. However, the increase in currents leads to the increase in the power dissipation, which is not preferable.